<%If Not Session("msg") = "" Then%>
<%=Session("msg")%>
<%Session("msg") = ""%>
<%End If%>
|
MEMORY COMPILERS
Single Port SRAM Compiler based on patented Glider Technology
The Single Port SRAM memory compiler utilizes our patented Glider technology and generates both normal and low voltage Single Port memories. The compiler has the following range of sizes: 4 to 4K words and 1 to 128 bits per word. Within these limits, the total Single Port SRAM size may vary between 4 and 128K total bits. Once a configuration is requested, the compiler will give the customer up to 3 versions from which to choose.
Dual Port SRAM Compiler based on patented CrossLink™ Technology
The Dual Port SRAM memory compiler utilizes our patented CrossLink™ technology. The compiler has the following range of sizes: 8 to 4K words and 1 to 128 bits per word. Within these limits, the total Dual Port SRAM size may vary between 8 and 128K total bits. Once a configuration is requested, the compiler will give the customer up to 3 versions from which to choose.
Dual Port R/W SRAM based on patented CrossLink™ Technology
The Dual Port R/W SRAM memories utilize our patented CrossLink™ technology. These hand crafted memories are 50% smaller than the competition while also decreasing the array power usage by 50%. Several configurations have already been proven in silicon.
|
|
 |
|
 |
|
All designs are created using standard layout logic. No layout cheats are used in any of our designs making Valence memories more manufacturable with a higher yield.
|
Valence, Inc was founded in 1993 specializing in embedded memory design. Our key personnel have over 33 years experience in leading-edge memories. We offer memory compilers, custom memories and design services.
|
CrossLink™ - patented technology
Valence has developed an innovative memory design that can substantially reduce the area of a memory. The reduced area is achieved through design techniques without compromising the robustness of the memory cell. By applying our patented CrossLink design to a traditional Dual Port SRAM we are able to reduce our memory cell size by 32%.
In addition to reducing your cost, CrossLink reduces array power, reduces sensing noise, improves performance and allows for a more robust design.
Glider - patented technology
Reduces array power, reduces sensing noise, improves performance and allows for a more robust design.
|
Questions? Comments? email
feedback@valence-inc.com
|
 |
|
 |
|
|
